x86/vhpet: add support for level triggered interrupts
authorRoger Pau Monné <roger.pau@citrix.com>
Tue, 24 Jul 2018 13:54:18 +0000 (15:54 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 24 Jul 2018 13:54:18 +0000 (15:54 +0200)
commitbe07023be115c94b7fbb51d2ef6f421ddd680de8
tree88513669009fdeaa98959553fcf82fc406187fbd
parent0bcbc971feaa7d9ef6d92b5b39a37819d449a821
x86/vhpet: add support for level triggered interrupts

Level triggered interrupts are not an optional feature of HPET, and
must be implemented in order to comply with the HPET specification.

Implement them by adding a callback to the timer which sets the
interrupt bit in the general interrupt status register. Further
interrupts (in case of periodic mode) will not be injected until the
bit is cleared.

In order to reset the interrupts when the status bit is clear Xen must
also detect accesses to such register.

While there convert tn and i in hpet_write to unsigned.

Reported-by: Stefan Bader <stefan.bader@canonical.com>
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/hvm/hpet.c
xen/arch/x86/hvm/irq.c
xen/include/asm-x86/hvm/irq.h